3-21 3-21 MT8809 8 x 8 analog switch array features ? internal control latches and address decoder ? short setup and hold times ? wide operating voltage: 4.5v to 13.2v ? 12vpp analog signal capability ?r on 65 w max. @ v dd =12v, 25 c ? d r on 10 w @ v dd =12v, 25c ? full cmos switch for low distortion ? minimum feedthrough and crosstalk ? low power consumption iso-cmos technology ? internal pull-up resistor for reset pin applications ? key systems ? pbx systems ? mobile radio ? test equipment/instrumentation ? analog/digital multiplexers ? audio/video switching description the mitel MT8809 is fabricated in mitels iso- cmos technology providing low power dissipation and high reliability. the device contains a 8 x 8 array of crosspoint switches along with a 6 to 64 line decoder and latch circuits. any one of the 64 switches can be addressed by selecting the appropriate six address bits. the selected switch can be turned on or off by applying a logical one or zero to the data input. chip select ( cs) allows the crosspoint array to be cascaded for matrix expansion. ordering information MT8809ae 28 pin plastic dip MT8809ap 28 pin plcc - 40 to 85 c figure 1 - functional block diagram 6 to 64 decoder latches 8 x 8 switch array ax0 ax1 ay0 ay1 ay2 str obe data reset vdd vss xi i/o (i=0-7) yi i/o (i=0-7) 11 64 64 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ax2 cs issue 2 november 1988 iso-cmos
MT8809 iso-cmos 3-22 figure 2 - pin connections pin description pin # name description 1ay2 ay2 address line (input) . 2 str obe strobe (input): enables function selected by address and data. address must be stable before str obe goes low and data must be stable on the rising edge of str obe. active low. 3 cs chip select (input): this is used to select the device. active low. 4 data data (input) : a logic high input will turn on the selected switch and a logic low will turn off the selected switch. active high. 5v ss ground reference. 6-9 x0, x2, x4, x6 x0, x2, x4 and x6 analog (inputs/outputs): these are connected to the x0, x2, x4 and x6 rows of the switch array. 10 reset master reset (input): this is used to turn off all switches regardless of the condition of cs. a 100k w internal pull-up resistor is also provided. this can be used in conjunction with a 0.1 m f capacitor (connected to the reset pin) to perform power-on reset of the device. active low. 11-18 y7 - y0 y7 - y0 analog (inputs/outputs): these are connected to the y0 - y7 columns of the switch array. 19 v dd positive power supply. 20-23 x7, x5, x3, x1 x7, x5, x3 and x1 analog (inputs/outputs): these are connected to the x7, x5, x3 and x1 rows of the switch array. 24-26 ax0-ax2 ax0 - ax2 address lines (inputs) . 27, 28 ay0, ay1 ay0 and ay1 address lines (inputs) . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 28 27 26 25 24 23 22 21 ay2 str obe cs data vss x0 x2 x4 x6 reset y7 y6 y5 y4 ay1 ay0 ax2 ax1 ax0 x1 x3 x5 x7 vdd y0 y1 y2 y3 28 pin plastic dip 4 5 6 7 8 9 10 11 25 24 23 22 21 20 19 data ax1 ax0 x1 x3 x5 x7 vdd vss x0 x2 x4 x6 reset y7 y1 3 2 1 28 27 26 12 13 14 15 16 17 18 cs str obe ay2 ay1 ay0 ax2 y6 y5 y4 y3 y2 y0 28 pin plcc
iso-cmos MT8809 3-23 functional description the MT8809 is an analog switch matrix with an array size of 8 x 8. the switch array is arranged such that there are 8 columns by 8 rows. the columns are referred to as the y inputs/outputs and the rows are the x inputs/outputs. the crosspoint analog switch array will interconnect any x i/o with any y i/o when turned on and provide a high degree of isolation when turned off. the control memory consists of a 64 bit write only ram in which the bits are selected by the address inputs (ay0-ay2, ax0-ax2). data is presented to the memory on the data input. data is asynchronously written into memory whenever both the cs (chip select) and str obe inputs are low and are latched on the rising edge of str obe. a logical 1 written into a memory cell turns the corresponding crosspoint switch on and a logical 0 turns the crosspoint off. only the crosspoint switches corresponding to the addressed memory location are altered when data is written into memory. the remaining switches retain their previous states. any combination of x and y inputs/outputs can be interconnected by establishing appropriate patterns in the control memory. a logical 0 on the reset input will asynchronously return all memory locations to logical 0 turning off all crosspoint switches regardless of whether cs is high or low. address decode the six address inputs along with the str obe and cs (chip select) are logically anded to form an enable signal for the resettable transparent latches. the data input is buffered and is used as the input to all latches. to write to a location, reset m ust be high and cs must go low while the address and data are set up. then the str obe input is set low and then high causing the data to be latched. the data can be changed while str obe is low, however, the corresponding switch will turn on and off in accordance with the data input. data must be stable on the rising edge of str obe in order for correct data to be written to the latch.
MT8809 iso-cmos 3-24 * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. ? dc electrical characteristics are over recommended temperature range. ? typical ?gures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. absolute maximum ratings * - voltages are with respect to v ss unless otherwise stated. parameter symbol min max units 1 supply voltage v dd v ss -0.3 -0.3 15.0 v dd +0.3 v v 2 analog input voltage v ina -0.3 v dd +0.3 v 3 digital input voltage v in v ss -0.3 v dd +0.3 v 4 current on any i/o pin i 15 ma 5 storage temperature t s -65 +150 c 6 package power dissipation plastic dip p d 0.6 w recommended operating conditions - voltages are with respect to v ss unless otherwise stated. characteristics sym min typ max units test conditions 1 operating temperature t o -40 25 85 c 2 supply voltage v dd 4.5 13.2 v 3 analog input voltage v ina v ss v dd v 4 digital input voltage v in v ss v dd v dc electrical characteristics ? - voltages are with respect to v ss =0v, v dd =12v unless otherwise stated. characteristics sym min typ ? max units test conditions 1 quiescent supply current i dd 1 100 m a all digital inputs at v in =v ss v dd except reset = v dd. 120 400 m a all digital inputs at v in =v ss or v dd except reset = v ss. 0.5 1.6 ma all digital inputs at v in =2.4v, v dd =5.0v 5 15 ma all digital inputs at v in =3.4v 2 off-state leakage current (see g.9 in appendix) i off 1 500 na iv xi - v yj i = v dd - v ss see appendix, fig. a.1 3 input logic 0 level v il 0.8 v 4 input logic 1 level v ih 3.0 v 6 input leakage (digital pins) i leak 0.1 10 m a all digital inputs at v in = v ss or v dd; reset = v dd dc electrical characteristics- switch resistance - v dc is the external dc offset applied at the analog i/o pins. characteristics sym 25 c70 c85 c units test conditions typ max typ max typ max 1 on-state v dd =12v resistance v dd =10v v dd = 5v (see g.1, g.2, g.3 in appendix) r on 45 55 120 65 75 185 75 85 215 80 90 225 w w w v ss =0v,v dc =v dd /2, iv xi -v yj i = 0.4v see appendix, fig. a.2 2 difference in on-state resistance between two switches (see g.4 in appendix) d r on 510 10 10 w v dd =12v, v ss =0, v dc =v dd /2, iv xi -v yj i = 0.4v see appendix, fig. a.2
iso-cmos MT8809 3-25 ? timing is over recommended temperature range. see fig. 3 for control and i/o timing details. ? typical ?gures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. crosstalk measurements are for plastic dips only, crosstalk values for plcc packages are approximately 5db better. ? timing is over recommended temperature range. see fig. 3 for control and i/o timing details. digital input rise time (tr) and fall time (tf) = 5ns. ? typical ?gures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. ? refer to appendix, fig. a.7 for test circuit. ac electrical characteristics ? - crosspoint performance - v dc is the external dc offset at the analog i/o pins. voltages are with respect to v dd =5v, v dc =0v, v ss =-7v, unless otherwise stated. characteristics sym min typ ? max units test conditions 1 switch i/o capacitance c s 20 pf f=1 mhz 2 feedthrough capacitance c f 0.2 pf f=1 mhz 3 frequency response channel on 20log(v out /v xi )=-3db f 3db 45 mhz switch is on; v ina = 2vpp sinewave; r l = 1k w see appendix, fig. a.3 4 total harmonic distortion (see g.5, g.6 in appendix) thd 0.01 % switch is on; v ina = 2vpp sinewave f= 1khz ; r l =1k w 5 feedthrough channel off feed.=20log (v out /v xi ) (see g.8 in appendix) fdt -95 db all switches off; v ina = 2vpp sinewave f= 1khz; r l = 1k w . see appendix, fig. a.4 6 crosstalk between any two channels for switches xi-yi and xj-yj. xtalk=20log (v yj /v xi ). (see g.7 in appendix). x talk -45 db v ina =2vpp sinewave f= 10mhz; r l = 75 w . -90 db v ina =2vpp sinewave f= 10khz; r l = 600 w . -85 db v ina =2vpp sinewave f= 10khz; r l = 1k w . -80 db v ina =2vpp sinewave f= 1khz; r l = 10k w . refer to appendix, fig. a.5 for test circuit. 7 propagation delay through switch t ps 30 ns r l =1k w ; c l =50pf ac electrical characteristics ? - control and i/o timings - v dc is the external dc offset applied at the analog i/o pins. voltages are with respect to v dd =5v, v dc =0v , v ss =-7v, unless otherwise stated. characteristics sym min typ ? max units test conditions 1 control input crosstalk to switch (for cs, data, str obe, address) cx talk 30 mvpp v in =3v+v dc squarewave; r in =1k w , r l =1k w . see appendix, fig. a.6 2 digital input capacitance c di 10 pf f=1mhz 3 switching frequency f o 20 mhz 4 setup time data to str obe t ds 10 ns r l = 1k w , c l =50pf ? 5 hold time data to str obe t dh 10 ns r l = 1k w , c l =50pf ? 6 setup time address to str obe t as 10 ns r l = 1k w , c l =50pf ? 7 hold time address to str obe t ah 10 ns r l = 1k w , c l =50pf ? 8 setup time cs to str obe t css 10 ns r l = 1k w , c l =50pf ? 9 hold time cs to str obe t csh 10 ns r l = 1k w , c l =50pf ? 10 str obe pulse width t spw 20 ns r l = 1k w , c l =50pf ? 11 reset pulse width t rpw 40 ns r l = 1k w , c l =50pf ? 12 str obe to switch status delay t s 40 100 ns r l = 1k w , c l =50pf ? 13 data to switch status delay t d 50 100 ns r l = 1k w , c l =50pf ? 14 reset to switch status delay t r 35 100 ns r l = 1k w , c l =50pf ?
MT8809 iso-cmos 3-26 figure 3 - control memory timing diagram * see appendix, fig. a.7 for switching waveform table 1. address decode truth table ay2 ay1 ay0 ax2 ax1 ax0 connection ay2 ay1 ay0 ax2 ax1 ax0 connection 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 x0 y0 x1 y0 x2 y0 x3 y0 x4 y0 x5 y0 x6 y0 x7 y0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 x0 y4 x1 y4 x2 y4 x3 y4 x4 y4 x5 y4 x6 y4 x7 y4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 x0 y1 x1 y1 x2 y1 x3 y1 x4 y1 x5 y1 x6 y1 x7 y1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 x0 y5 x1 y5 x2 y5 x3 y5 x4 y5 x5 y5 x6 y5 x7 y5 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 x0 y2 x1 y2 x2 y2 x3 y2 x4 y2 x5 y2 x6 y2 x7 y2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 x0 y6 x1 y6 x2 y6 x3 y6 x4 y6 x5 y6 x6 y6 x7 y6 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 x0 y3 x1 y3 x2 y3 x3 y3 x4 y3 x5 y3 x6 y3 x7 y3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 x0 y7 x1 y7 x2 y7 x3 y7 x4 y7 x5 y7 x6 y7 x7 y7 cs reset str obe address data switch* t css t csh t rpw t spw t as t ah t ds t dh t d t s t r t r on off 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50%
package outlines plastic j-lead chip carrier - p-suf?x f d 1 d h e 1 i a 1 a g d 2 e e 2 dim 20-pin 28-pin 44-pin 68-pin 84-pin min max min max min max min max min max a 0.165 (4.20) 0.180 (4.57) 0.165 (4.20) 0.180 (4.57) 0.165 (4.20) 0.180 (4.57) 0.165 (4.20) 0.200 (5.08) 0.165 (4.20) 0.200 (5.08) a 1 0.090 (2.29) 0.120 (3.04) 0.090 (2.29) 0.120 (3.04) 0.090 (2.29) 0.120 (3.04) 0.090 (2.29) 0.130 (3.30) 0.090 (2.29) 0.130 (3.30) d/e 0.385 (9.78) 0.395 (10.03) 0.485 (12.32) 0.495 (12.57) 0.685 (17.40) 0.695 (17.65) 0.985 (25.02) 0.995 (25.27) 1.185 (30.10) 1.195 (30.35) d 1 /e 1 0.350 (8.890) 0.356 (9.042) 0.450 (11.430) 0.456 (11.582) 0.650 (16.510) 0.656 (16.662) 0.950 (24.130) 0.958 (24.333) 1.150 (29.210) 1.158 (29.413) d 2 /e 2 0.290 (7.37) 0.330 (8.38) 0.390 (9.91) 0.430 (10.92) 0.590 (14.99) 0.630 (16.00) 0.890 (22.61) 0.930 (23.62) 1.090 (27.69) 1.130 (28.70) e 0 0.004 0 0.004 0 0.004 0 0.004 0 0.004 f 0.026 (0.661) 0.032 (0.812) 0.026 (0.661) 0.032 (0.812) 0.026 (0.661) 0.032 (0.812) 0.026 (0.661) 0.032 (0.812) 0.026 (0.661) 0.032 (0.812) g 0.013 (0.331) 0.021 (0.533) 0.013 (0.331) 0.021 (0.533) 0.013 (0.331) 0.021 (0.533) 0.013 (0.331) 0.021 (0.533) 0.013 (0.331) 0.021 (0.533) h 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) 0.050 bsc (1.27 bsc) i 0.020 (0.51) 0.020 (0.51) 0.020 (0.51) 0.020 (0.51) 0.020 (0.51) notes: 1) not to scale 2) dimensions in inches 3) (dimensions in millimeters) 4) for d & e add for allowable mold protrusion 0.010" e: (lead coplanarity) general-10
package outlines plastic dual-in-line packages (pdip) - e suf?x note: controlling dimensions in parenthesis ( ) are in millimeters. dim 8-pin 16-pin 18-pin 20-pin plastic plastic plastic plastic min max min max min max min max a 0.210 (5.33) 0.210 (5.33) 0.210 (5.33) 0.210 (5.33) a 2 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) 0.115 (2.92) 0.195 (4.95) b 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) b 2 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) 0.045 (1.14) 0.070 (1.77) c 0.008 (0.203) 0.014 (0.356) 0.008 (0.203) 0.014(0.356) 0.008 (0.203) 0.014 (0.356) 0.008 (0.203) 0.014 (0.356) d 0.355 (9.02) 0.400 (10.16) 0.780 (19.81) 0.800 (20.32) 0.880 (22.35) 0.920 (23.37) 0.980 (24.89) 1.060 (26.9) d 1 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) e 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) 0.300 (7.62) 0.325 (8.26) e 1 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) 0.240 (6.10) 0.280 (7.11) e 0.100 bsc (2.54) 0.100 bsc (2.54) 0.100 bsc (2.54) 0.100 bsc (2.54) e a 0.300 bsc (7.62) 0.300 bsc (7.62) 0.300 bsc (7.62) 0.300 bsc (7.62) l 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) 0.115 (2.92) 0.150 (3.81) e b 0.430 (10.92) 0.430 (10.92) 0.430 (10.92) 0.430 (10.92) e c 0 0.060 (1.52) 0 0.060 (1.52) 0 0.060 (1.52) 0 0.060 (1.52) e 1 32 1 e n-2 n-1 n l d d 1 b 2 a 2 e b c e a notes: 1) not to scale 2) dimensions in inches 3) (dimensions in millimeters) a e b e c general-8
package outlines plastic dual-in-line packages (pdip) - e suf?x dim 22-pin 24-pin 28-pin 40-pin plastic plastic plastic plastic min max min max min max min max a 0.210 (5.33) 0.250 (6.35) 0.250 (6.35) 0.250 (6.35) a 2 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) 0.125 (3.18) 0.195 (4.95) b 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) 0.014 (0.356) 0.022 (0.558) b 2 0.045 (1.15) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) 0.030 (0.77) 0.070 (1.77) c 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) 0.008 (0.204) 0.015 (0.381) d 1.050 (26.67) 1.120 (28.44) 1.150 (29.3) 1.290 (32.7) 1.380 (35.1) 1.565 (39.7) 1.980 (50.3) 2.095 (53.2) d 1 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) 0.005 (0.13) e 0.390 (9.91) 0.430 (10.92) 0.600 (15.24) 0.670 (17.02) 0.600 (15.24) 0.670 (17.02) 0.600 (15.24) 0.670 (17.02) e 0.290 (7.37) .330 (8.38) e 1 0.330 (8.39) 0.380 (9.65) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73) 0.485 (12.32) 0.580 (14.73) e 1 0.246 (6.25) 0.254 (6.45) e 0.100 bsc (2.54) 0.100 bsc (2.54) 0.100 bsc (2.54) 0.100 bsc (2.54) e a 0.400 bsc (10.16) 0.600 bsc (15.24) 0.600 bsc (15.24) 0.600 bsc (15.24) e a 0.300 bsc (7.62) e b 0.430 (10.92) l 0.115 (2.93) 0.160 (4.06) 0.115 (2.93) 0.200 (5.08) 0.115 (2.93) 0.200 (5.08) 0.115 (2.93) 0.200 (5.08) a 15 15 15 15 e 1 32 1 e n-2 n-1 n l d d 1 b 2 a 2 e b c e a notes: 1) not to scale 2) dimensions in inches 3) (dimensions in millimeters) a e b a shaded areas for 300 mil body width 24 pdip only
m mitel (design) and st-bus are registered trademarks of mitel corporation mitel semiconductor is an iso 9001 registered company copyright 1999 mitel corporation all rights reserved printed in canada technical documen t a tion - n o t for resale world headquarters - canada tel: +1 (613) 592 2122 fax: +1 (613) 592 6909 north america asia/paci?c europe, middle east, tel: +1 (770) 486 0194 tel: +65 333 6193 and africa (emea) fax: +1 (770) 631 8213 fax: +65 333 6192 tel: +44 (0) 1793 518528 fax: +44 (0) 1793 518581 http://www.mitelsemi.com information relating to products and services furnished herein by mitel corporation or its subsidiaries (collectively mitel) is believed to be reliable. however, mitel assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by mitel or licensed from third parties by mitel, whatsoever. purchasers of products are also hereby noti?ed that the use of product in certain ways or in combination with mitel, or non-mitel furnished goods or services may infringe patents or other intellectual property rights owned by mitel. this publication is issued to provide information only and (unless agreed by mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, their speci?cations, services and other information appearing in this publication are subject to change by mitel without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a speci?c piece of equipment. it is the users responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in signi?cant injury or death to the user. all products and materials are sold and services provided subject to mitels conditions of sale which are available on request.
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